Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitate careful process monitoring, including frequent and detailed inspection of the devices while they are still in the form of semiconductor wafers.
A conventional in-process monitoring technique employs a two phase “inspection and review” procedure. During the first phase, the surface of the wafer is inspected at high-speed and relatively low-resolution. The purpose of the first phase is to produce a defect map showing suspected locations on the wafer having a high probability of a defect. During the second phase the suspected locations are more thoroughly analyzed. Both phases may be implemented by the same device, but this is not necessary.
The two phase inspection tool may have a single detector or multiple detectors. Multiple detector two phase inspection devices are described, by way of example, in U.S. Pat. Nos. 5,699,447, 5,982,921, and 6,178,257.
FIG. 1 is an illustration of a wafer 10 such as ones which may be used in the fabrication of integrated circuits and other microdevices. While the term wafer may be used to refer only to the substrate material on which the integrated circuit is fabricated (e.g. a thin slice of semiconductor material, such as a silicon crystal), this term may also be used to refer to the entire construction, including the electronic circuit fabricated on the wafer.
The wafer 10 is divided into multiple dies 11 which are illustrated in a widely implemented rectangular form. Like the term ‘wafer’, the term ‘die’ may also be used either for small blocks of semiconducting material, on which a given functional circuit is fabricated, or for such a block including the fabricated electric circuit. Usually, wafer 10 may be cut (“diced”) into its multiple dies 11, wherein all of the dies of the wafer contain a copy of the same electronic circuit. While not necessarily so, each of the dies 11 is independently functional.
A single die may include a large amount of patterns that well exceed millions of patterns per die. A semiconductor die usually includes a plurality of layers. A pattern, such as local pattern 24 may be a part of a metal interconnection line, a trench, a via, a conductive gate, etc. Different areas on each die may be put to different uses; such areas may be for example background areas (that are ideally very smooth), memory areas (that include a large number of repetitive patterns) and logic areas (that usually do not include large quantities of adjacent repetitive patterns).
FIG. 2 illustrates a portion of an inspection image of an electric circuit (which may be manufactured on a wafer) which is repetitive in nature. While not necessarily so, portion 12 illustrated in FIG. 2 may represent a part of a single die 11. It is noted that the inspection image to which the herein disclosed systems and methods pertain may be any inspection image that is generated by collecting signals arriving from the inspected object (e.g. electromagnetic signals, reflected images, etc.).
Portion 12 shows 20 cells (a singled out cell is denoted 13 in the drawing and is framed with a broken-line) which are arranged in a 4 by 5 array, wherein the content of the cells are similar to each other. Each of the small squares within each cell (whether black or white) represents a single pixel. The bold lines surrounding each cell (whose size is 8×8 pixels) are presented for the sake of illustration only.
In the illustration of FIG. 2, the image is a binary image in which each pixels may have one out of two possible values (represented by black and white pixels). However, in other implementations (e.g. as in many machines used for wafer inspection and mask inspection), richer color depth may be used (e.g. 256 possible values for each pixel).
While the cells of FIG. 2 are identical to each other, it is clear that in a real life scan image of an actual object, e.g. wafer, the cells may be somewhat different from each other. Some of these differences are not indicative of defects (e.g. scanning errors, illumination defects, or even manufacture inaccuracies which do not mount to a defect nor do they render the electric circuit faulty), while other differences may be indicative of an actual defect which is to be detected.
Prior art Cell-to-Cell comparison techniques include the comparing of a pixel of one cell to a corresponding pixel of one other cell (e.g. an adjacent one), and based on the difference between these two values, determining whether there is a possible defect in that pixel or not.
There exists a need for improved and more robust techniques for detecting defects in a substrate, and especially in a semiconductor substrate.